Computer systems generally comprise a processor which executes program routines from memory and operates on data stored in memory. The execution of a program routine may be interrupted, for example, by means of an external interrupt signal, to cause the processor to begin execution of a so-called interrupt routine. Before the processor begins the execution of the interrupt routine, however, it stores certain information, which represents the operational state of the processor and which is referred to as the processor context, in an area of memory called the interrupt stack. Upon completion of the interrupt routine, the processor retrieves the context information from memory to restore the processor to the operational state existing before the interrupt and resumes processing of the interrupted routine.
Modern computer systems employ processors which are capable of operating at much higher rates of execution than large capacity main memories can support, and a low capacity, high-speed cache memory is commonly used in addition to a large capacity main memory to improve program execution speed. The cache memory stores a limited number of instructions or data words; and for each memory read operation, a control circuit associated with the cache memory will check the cache memory to determine if the information is available in the cache memory, otherwise the processor will read the main memory. Memory write operations generally cause information to be written simultaneously in the cache and the main memory. Main memory access times generally are substantially greater than cache memory access time, and it is well recognized that in normal operations the addition of a cache memory saves a substantial amount of processor time.
The context information usually consists of several data words and the storing and retrieving of context information tends to create a significant demand on processor time, particularly, in the event of high interrupt activity. To alleviate this burden, some prior art processing systems store the context information in the cache memory. While this may decrease the amount of time required to read context information after the interrupt has been serviced, it does not decrease the time required to store the information since it must be written into the main memory as well as the cache memory. Furthermore, since the context information can be replaced by other data, it may not be available in the cache memory when it is needed. In that case, the context information must be read from the main memory and no advantage has been gained from storing the information in the cache memory.
For many applications, including the addressing of the interrupt stack, it is desirable to use the virtual addressing technique. By this technique, a program specifies a virtual address which is a reference to a defined real memory location but which by itself does not define the real memory location. When virtual addressing is used, a virtual address to real address translation must be made, and unless translation circuitry, such as an address translation buffer, is used, virtual addressing of the interrupt stack will further increase the real-time burden on the processor associated with interrupt activity.